Erasable programmable read only memories (EPROMs) and electrically erasable programmable read only (EEPROMs) are well known in the art. These devices have the ability to store data in non-volatile fashion, while also being capable of being erased and rewritten as desired. EPROM devices are typically erased by exposing the integrated circuit device to ultraviolet radiation, while EEPROMs allow erasure to be performed electrically.
One form of EEPROM device includes a so-called "split-gate" electrode, in which the control gate includes a first portion overlaying a floating gate and a second portion directly overlaying the channel. Such a split gate structure is described in a 5-Volt-Only Fast-Programmable Flash EEPROM Cell with a Double Polysilicon Split-Gate Structure by J. Van Houdt et al, Eleventh IEEE Non-Volatile Semiconductor Workshop, February 1991, in which charge is injected into the floating gate from the source side of the cell. U.S. Pat. No. 4,652,897 describes an EEPROM device which does not utilize a split-gate, but which also provides injection to the floating gate from the source side of the device.
As described in the above referenced U.S. Pat. No. 4,652,897, memory cells are typically arranged in an array, as is well known in the art. One form of such an array utilizes buried diffusions, in which source and array regions are covered with a fairly thick layer of insulating material. This is shown for example, in U.S. Pat. Nos. 4,151,020; 4,151,021; 4,184,207; and 4,271,421. Such buried diffusion devices often utilize a virtual ground approach, in which columns connecting the sources of a first column of memory cells also serves to connect drains of an adjacent column of memory cells.
While many EEPROM devices utilize two layers of polycrystalline silicon, one for the formation of the floating gate, and the other for the formation of the control gate and possibly electrical interconnects, other EEPROM devices utilize three layers of polycrystalline silicon. For example, U.S. Pat. No. 4,302,766 provides a first polycrystalline silicon layer for the floating gate, a second polycrystalline silicon layer for the control gate, and a third polycrystalline silicon layer coupled through an erase window to a portion of the first polycrystalline silicon layer for use during erasure of the cell. U.S. Pat. No. 4,331,968 also uses a third layer of polycrystalline silicon to form an erase gate, while U.S. Pat. No. 4,462,090 forms an addressing gate electrode utilizing a third layer of polycrystalline silicon. U.S. Pat. Nos. 4,561,004 and 4,803,529 also use three layers of polycrystalline silicon in their own specific configurations.
Japanese Patent Publication 61-181168 appears to utilize three layers of polycrystalline silicon to provide additional capacitive coupling to the floating gate. Japanese Patent Publication 63-265391 appears to pertain to a buried diffusion array, possibly utilizing virtual grounds.
European Patent Application 0373830 describes an EEPROM in which two polycrystalline silicon layers are used, with the second layer of polycrystalline silicon having two pieces, one of which provides the erase function, and one of which provides the steering function.
"A New Flash-Erase EEPROM Cell With a Sidewall Select-Gate on its Source Side" by K. Naruke et al. IEDM-89-603 and U.S. Pat. No. 4,794,565 describe an EEPROM utilizing a side wall select gate located on the source side of the field effect transistor.
"EPROM Cell With High Gate Injection Efficiency" by M. Kamiya et al. IEDM 82-741, and U.S. Pat. No. 4,622,656 describe an EEPROM device in which a reduced programming voltage is provided by having a highly doped channel region under the select gate, and the channel region under the floating gate being either lightly doped or doped to the opposite conductivity type, thereby providing a significant surface potential gap at the transition location of the channel.